1. Field of the Invention
The present disclosure relates to the field of semiconductor manufacturing, and, more particularly, to the formation of a semiconductor device which has a reduced tendency to generate electrical shorts through contact ILD voids.
2. Description of the Related Art
Modern integrated circuits comprise a large number of circuit elements, such as resistors, capacitors, transistors and the like. Typically, these circuit elements are formed on and in a semiconductor layer, such as a silicon layer, wherein it is usually necessary to substantially electrically isolate adjacent semiconductor regions from each other in which the individual circuit elements are formed. A representative example in this respect is a field effect transistor, the active area of which, i.e., the highly doped drain and source regions with an inversely lightly doped channel region disposed therebetween, is defined by an isolation structure formed in the semiconductor material.
Since the critical feature sizes of the circuit elements, such as the gate length of field effect transistors, are steadily decreasing, the area enclosed by the isolation structures, as well as the isolation structures themselves, is also reduced in size. Among the various techniques for forming the isolation structures, the so-called shallow trench isolation (STI) technique has proven to be the most reliable method and has become the most frequently used technique for forming isolation structures for sophisticated integrated circuits.
According to the STI technique, individual circuit elements are insulated from each other by shallow trenches etched into the semiconductor material. This semiconductor material may be a semiconductor substrate, when bulk semiconductor devices are considered. Alternatively, a semiconductor layer may be formed on an insulating substrate, as is the case, for example, for silicon-on-insulator (SOI) substrates, in which the circuit elements are formed. The trenches are subsequently filled with a dielectric material, such as an oxide, to provide the required electrical insulation of adjacent circuit elements.
On the other hand, the circuit elements need to be electrically contacted. A typical example of such an electrical contact in the fabrication of semiconductor devices is the formation of contact plugs, wherein openings extending through an interlayer dielectric (ILD) are filled with a conductive material in order to electrically connect to the respective circuit element. A bottom region and sidewall region of the opening is usually provided with an appropriate intermediate layer, that is, a conductive layer, so that subsequently deposited conductive material exhibits good adhesion to the surrounding dielectric layer, and undue interaction of the conductive material with the surrounding dielectric layer may be avoided during processing as well as during operation of the semiconductor device. In advanced semiconductor devices, the interconnect plugs are typically formed of a tungsten-based metal that are provided in an interlayer in the electric stack, which is typically comprised of silicon dioxide, including a bottom etch stop layer typically formed of silicon nitride.
In modern integrated circuits, openings (so-called vias) are formed exhibiting an aspect ratio that may be as high as approximately 8:1 or more, and the opening may have a diameter of 0.1 μm or smaller. Further, the high integration and the close packing of circuit elements, in particular the close packing of field effect transistors, also leads to a high aspect ratio between the gate electrodes of neighboring transistors. The etch stop layer formed above the circuit elements increases the aspect ratio even further. Therefore, in highly integrated circuits, the ILD deposition is not able to fill the originated gap between neighboring circuit elements, for example, between neighboring gate electrodes of field effect transistors, and thus causes a void along adjacent gates.
With reference to FIGS. 1A-1D, a typical conventional process for manufacturing contacts to neighboring circuit elements in accordance with a well-established tungsten technology will now be described in more detail in order to illustrate the problems involved in the formation of a reliable and high yield semiconductor device.
FIG. 1A schematically shows a semiconductor device 100 during a manufacturing stage for the formation of a contact interlayer dielectric above two neighboring circuit elements, such as transistors 110 formed above an appropriate semiconductor substrate 101. Each circuit element 110 may comprise one or more contact regions, such as a contact region of a gate electrode 111, and of drain and source regions 112. The contact regions may comprise a silicide portion 111A, 112A which provides a good and reliable electrical contact. The circuit elements 110 are covered by a dielectric material which may comprise a contact etch stop layer 102, which may be formed of silicon nitride. The circuit elements 110 are electrically isolated by a shallow trench isolation 114. The shallow trench isolation 114 may be slightly recessed with respect to the contact regions 112A of the source and drain regions 112. Although, in an initial manufacturing stage, the shallow trench isolation is planarized with the surface of the semiconductor layer 101, the slight recessing of the STI may occur due to material removal from the STI during manufacturing of the circuit elements 110, e.g., by etch or cleaning processes.
In highly integrated circuits, as shown in FIG. 1A, the small distance between the gate electrodes 111 of the circuit elements 110 leads to a high aspect ratio of the gap 116 between the gate electrodes 111. The etch stop layer 102, as well as the slight recess of the shallow trench isolation 114, further enhances this high aspect ratio.
FIG. 1B shows the semiconductor device 100 of FIG. 1A in a further advanced manufacturing stage, wherein silicon dioxide 103 is deposited on the etch stop layer 102 on the basis of well-known techniques, e.g., plasma enhanced chemical vapor deposition (PECVD) techniques, e.g., on the basis of TEOS (tetraethylorthosilicate, Si(OC2H5)4), thereby providing a dense and compact material layer.
It was found by the inventors that, for narrow gaps 116, the deposition process of the interlayer dielectric 103 is not capable of filling these gaps 116 completely, but rather a void 118 develops as is schematically shown in FIG. 1C, which shows a further advanced manufacturing step of the semiconductor device 100. It should be noted that FIGS. 1A-1D are not drawn to scale but are exaggerated to some extent for illustration purposes.
FIG. 1D shows the semiconductor device 100 in a further advanced manufacturing stage. Herein, the formation of the interlayer dielectric layer 103 has been completed. Further, after any optional planarization processes for planarizing the layer 103, a photolitho-graphic sequence has been performed on the basis of well-established techniques, followed by anisotropic etch techniques and recipes for forming the contact openings 104 in the layer 103. The etch process for forming the contact openings 104 may be reliably controlled on the basis of the etch stop layer 102. Thereafter, a further etch process may be performed to finally open the contact etch stop layer 102 on the basis of well-established techniques. Thereafter the titanium layer, e.g., a Ti/TiN layer may be formed on the basis of ionized physical vapor deposition, such as sputter deposition 105. The term “sputtering” or “sputter deposition” describes a mechanism in which atoms are ejected from a surface of a target material upon being hit by sufficiently energetic particles. Although, in principle, the barrier layer 105 may be formed by using chemical vapor deposition (CVD) techniques, sputter deposition is widely used for the deposition of the barrier layer 105 for the following reasons.
Sputter deposition allows relatively uniform deposition of layers over large area substrates, since sputtering may be accomplished from large-area targets. Control of film thickness by sputter deposition is relatively simple as compared to CVD deposition and may be achieved by selecting a constant set of operating conditions, wherein the deposition time is adjusted to achieve the required film thickness. Moreover, the composition of compounds, such as titanium nitride used in the barrier layer 105, may be controlled more easily and precisely in sputter deposition processes as compared to CVD. Additionally, the surfaces of the substrates to be processed may be sputter cleaned prior to the actual film deposition so that any contamination of the surface may be efficiently removed and further recontamination prior to the actual deposition process may be effectively suppressed. For an efficient deposition of a moderately thin material within the contact openings 104 having a moderately high aspect ratio, so-called ionized sputter deposition techniques are used in which target atoms liberated from the target are efficiently ionized by a respective plasma ambient while moving towards the substrate. On the basis of a DC or RF bias, the directionality of the moving ionized target atoms may be significantly enhanced, thereby enabling the deposition of target material at the bottom of the contact openings 104 even for high aspect ratios.
As shown in FIG. 1D, the void 118 formed in the interlayer dielectric layer 103 is opened by two neighboring contact openings 104. The subsequent Ti/TiN barrier cannot seal the opening 120 in the contact via 104. Therefore, the following deposition of tungsten 122 fills (at least in part) the void 118 and causes an electrical short between neighboring contacts. Such an electrical short reduces the overall yield.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.